In this type of system it is common to add a few extra bits in the so-called cell header in order to protect the information it contains. In the case of CCITT Recommendations G.707, G.708 and G.709, a fifth byte of redundant information is added to the four initial bytes in the ATM cell header. This fifth byte is termed the protection byte and is produced by means of a cyclic coding with a cyclic code (40, 32) generated by the polynomial g(X)=X.sup.8 +X.sup.2 +X+1.
To extract the error-free initial information, these cyclic codes have to be decoded. One of the decoding methods for cyclic codes is that described in the book "Error Correcting Codes" by W. W. Peterson, published by the Massachusetts Institute of Technology and John Wiley & Sons, Inc., New York and London, 1961, pages 201-204.
The method consists in applying the coded data vector to a divider circuit based on a Meggit Decoder with serial data input and, simultaneously, to a storage register.
The divider circuit, which includes a shift register, calculates the so-called "snydrome", such that there is a one-on-one correspondence between this syndrome and the error pattern that is assumed to have occurred. The combinational logic circuit, that is connected to the outputs of the shift register, is designed to have a "1" at its output if, and only if, the syndrome obtained from the divider circuit corresponds to an error pattern with an error in the next bit to leave the storage register.
The storage register must first contain an initial value for a correct decoding, which for this particular case, is all registers set to "0", corresponding also to the initial value of the shift register in the polynomial generator used by the CCITT Recommendations mentioned earlier.
The output of the divider circuit can be expressed in matrixial form as: EQU S.sub.ts+1 =T.multidot.S.sub.ts +U.sub.ts,
where
S.sub.ts is the output of the codes vector from the shift register in the divider circuit, at the time ts, PA1 S.sub.ts+1 is the output of the codes vector at the time ts+1, PA1 T is a square matrix that represents the codes transformation of the serial divider circuit (transformation matrix), and PA1 U.sub.ts is the input vector to the shift register at the time ts. PA1 T.sup.n is the n-th power of the serial transformation matrix; PA1 U.sub.tp is the n-bit input data vector at time tp; PA1 S.sub.tp is the syndrome word at time tp; and PA1 S.sub.tp+1 is the syndrome word at time tp+1; PA1 that no error has been detected; or PA1 that more than one error has been detected; or PA1 the erroneous bit to be corrected when only one error has been detected.
This systematic method works at the same rate as the binary data rate and produces, at its output, the syndrome corresponding to the current input.
The main drawback of this type of method that works in series, in addition to the limitation in the type of integration technology to be used with present-day communications systems which work at increasingly faster speeds, is that the power consumption of devices working in series, whether at current speeds or at speeds foreseen for the near future, can reach levels that are unacceptable in practice.